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hi-8435 32-channel ground/open or supply/open sensor with spi interface general description features the hi-8435 is a 32-channel discrete-to-digital sensor fabricated with silicon-on-insulator (soi) technology designed to interface with a serial peripheral interface (spi). four banks of 8 sense inputs the sensing circuit window comparator thresholds are set by programming the center threshold and hysteresis registers to values from 2v to 22v. the digital values of the sensed inputs can be read either one bank at a time or all 4 banks with one command. each bank of sensors have a vwetn pin available for optional application of a voltage higher than the logic supply to provide wetting current to ground side relay contacts. if the ground offset is small, then the wetting source will automatically be provided from vlogic without connecting vwetn. interface to the digital subsystem is simple cmos logic inputs and outputs. the logic pins are compatible with 3.3v logic allowing direct connection to a wide range of microcontrollers or fpgas. can be programmed as either gnd/open or supply/open sensors. supply/open sensing is also referred to as 28v/open sensing. all sense inputs are internally lightning protected to do160g, section 22, cat az, bz and zz without external components. robust cmos silicon-on-insulator (soi) technology 32-channel programmable sense operation, gnd/open or supply/open, 4 x 8 input sensors programmable hi/lo threshold and hysteresis in 0.5v steps, from 2v to 22v. single low voltage supply operation for low thresholds applications. logic operation from 3.0v to 3.6v 20 mhz serial peripheral interface (spi) lightning protected sense inputs airbus abd0100h compliant mil-std-704 compliant internal self-test july 2013 44 pin plastic quad flat pack (pqfp) 10mm x 10mm pin configurations application avionics discrete to digital sensing holt integrated circuits (ds8435 rev. c) 07/13 www.holtic.com 44 - vlogic 43 - sck 42 - csn 41 - si 40 - so 39 - mrb 38 - gnd 37 - sense_31 36 - sense_30 35 - sense_29 34 - sense_28 33 - sense_27 32 - vwet3 31 - sense_26 30 - sense_25 29 - sense_24 28 - sense_23 27 - sense_22 26 - sense_21 25 - sense_20 24 - sense_19 23 - sense_18 vwet1 - 12 nc - 13 sense_10 - 14 sense_11 - 15 sense_12 - 16 sense_13 - 17 sense_14 - 18 sense_15 - 19 sense_16 - 20 sense_17 - 21 vwet2 - 22 vwet0 - 1 sense_0 - 2 sense_1 - 3 sense_2 - 4 sense_3 - 5 sense_4 - 6 sense_5 - 7 sense_6 - 8 sense_7 - 9 sense_8-10 sense_9-11 hi-8435pqi hi-8435pqt 44 pin plastic qfn 7mm x 7mm vwet1 - 12 nc-13 sense_10 - 14 sense_1 1-15 sense_12 - 16 sense_13 - 17 sense_14 - 18 sense_15 - 19 sense_16 - 20 sense_17 - 21 vwet2 - 22 44 - vlogic 43 - sck 42 - csn 41-si 40-so 39 - mrb 38 - gnd 37 - sense_31 36 - sense_30 35 - sense_29 34 - sense_28 vwet0 - 1 sense_0 - 2 sense_1 - 3 sense_2 - 4 sense_3 - 5 sense_4 - 6 7 sense_6 - 8 sense_7 - 9 sense_8 -10 sense_9 -11 sense_5 - 33 - sense_27 32 - vwet3 31 - sense_26 30 - sense_25 29 - sense_24 28 - sense_23 27 - sense_22 26 - sense_21 25 24 - sense_19 23 - sense_18 - sense_20 hi-8435pc
block diagram hi-8435 holt integrated circuits 2 spi mrb psen_n psen_n vlogic gnd so csn sck vwet0-3 v logic figure 2. si pd hi lo testhi v logic testlo + - + - psen_n vref dac thresholds pu hi lo sense_7-0 8 8 8 sense_15-8 sense_23-16 sense_31-24 8 8 8 8 so_7-0 so_15-8 so_23-16 so_31-24 32 so_31-0 4 test 12 psen_3-0 dac value/hysteresis 4 vthi/10 vthi/10 360k 40k lightning protection v logic vwet0 23.8k 3.3k 29k 50k
holt integrated circuits 3 pin function description vlogic supply 3.3v power supply for both sensors and logic. vwet<0-3> supply optional inputs to supply relay wetting current to sense lines in gnd/open operation. each of the 4 banks of 8 inputs has a vwetn pin. 50k to gnd. sense<31:0> discrete input 4 banks of 8 discrete inputs programmable through the spi to be either gnd/open or supply/open. the type of input is programmed by bank, psen<3:0> bits. 0 makes the bank gnd/open sensors, 1 makes the bank supply/open sensors the status of the inputs sense<31:0> are stored in so<31:0> see spi section for programming and reading sensors. gnd supply 0v ground for sensor and logic. sck digital input spi clock. csn digital input spi chip select, active low, internal 30k pull-up. si digital input spi serial data input, internal 30k pull-down. so digital output spi serial data output. mrb digital input master reset bar, active low, internal 30k pull-up. hi-8435 pin descriptions op code r/w # data bytes description 0x02 w 1 write control register 0x04 w 1 write program sense banks register, psen<3:0>, to program sense inputs 0x3a w 2 write gnd/open threshold center value and hysteresis 0x3c w 2 write supply/open threshold center value and hysteresis 0x1e w 1 write test mode data register 0x82 r 1 read control register 0x84 r 1 read program sense banks register, to read programmed bank type 0xba r 2 read gnd/open threshold center value and hysteresis 0xbc r 2 read supply/open threshold center value and hysteresis 0x9e r 1 read test mode data register 0x90 r 1 read bank 0, sout register, so<7:0>, status of sense<7:0> inputs 0x92 r 1 read bank 1, sout register, so<15:8>, status of sense<15:8> inputs 0x94 r 1 read bank 2, sout register, so<23:16>, status of sense<23:16> inputs 0x96 r 1 read bank 3, sout register, so<31:24>, status of sense<31:24> inputs 0xf8 r 4 read all banks, sout register, so<31:0>, status of sense<31:0> inputs spi commands table 2. table 1.
hi-8435 spi instructions figure 5 to figure 7 show read and write timing for single-byte, dual-byte and four byte register operations. the instruction op code is immediately followed by data bytes comprising the 8-bit data bytes read or written. for a register read or write, csn is negated after all data bytes are transferred. table 2 summarizes the hi-8435 spi instruction set. the spi instructions used to read, write and configure the hi-8435 consist of an opcode and data bytes. each spi instruction begins with an 8-bit opcode with the format shown below. the most significant bit (msb) specifies whether the instruction is a write, 0, or a read, 1, transfer. when csn goes low, the first 8 rising edges of the sck shift the op code into the decoder register, msb first. the spi can be clocked up to 20 mhz. for write instructions, the next 8 rising sck edges shift a data byte into the buffer register. the specific instruction register is loaded on the 8th rising sck edge. this sequence is repeated until the required number of data bytes for the instruction are written. for read instructions, the most significant bit of the requested data word appears at the so pin at the next falling sck edge after the last op code bit is clocked into the decoder. as in write instructions, the number of data bytes varies with read the instruction. so data changes on the falling sck edges. x x x xx figure 4. spi opcode format 76543210 msb lsb x x r/w msb lsb msb lsb high z high z csn so si sck (spi mode 0) figure 3. generalized single-byte transfer using spi protocol mode 0 serial peripheral interface (spi) spi basics the hi-8435 uses a spi (serial peripheral interface) for host access to internal registers which program the chip and store sensor status. host serial communication is enabled through the active low, chip select (csn) pin, and is accessed via a four-wire interface consisting of serial data input (si) from the host, serial data output (so) to the host, the serial clock (sck) and the csn. all read / write cycles are completely self- timed. the spi protocol specifies master and slave operation; the hi-8435 operates as a spi slave. the spi protocol defines two parameters, cpol (clock polarity) and cpha (clock phase). the possible cpol-cpha combinations define four possible spi modes. without describing details of the spi modes, the hi-8435 operates in mode 0 where input data for each device (master and slave) is clocked on the rising edge of sck, and output data for each device changes on the falling edge (cpha = 0, cpol = 0). the host spi logic be set for mode 0 for proper communications with the hi-8435. as seen in figure 3, spi mode 0 holds sck in the low state when idle. the spi protocol transfers serial data in 8-bit bytes. once csn is asserted, the rising edge of sck shifts the input data into the master and slave devices, starting with each byte's most-significant bit. a rising edge on csn completes the serial transfer and re-initializes the hi-8435 spi for the next transfer. if csn goes high before a full byte is clocked by sck, the incomplete byte clocked into the device si pin is discarded. in the general case, both master and slave simultaneously send and receive serial data (full duplex), per figure 3 below. however the hi-8435 operates half duplex, maintaining high impedance on the so output, except when actually transmitting serial data. when the hi-8435 is sending data on so during read operations, activity on its si input is ignored. the host likewise ignores its si input activity while transmitting to the hi- 8435. must holt integrated circuits 4 hi-8435
figure 5. single-byte read from a register csn so si sck msb lsb 0 12 3 4 5 67 high z high z 0 12 3 4 5 67 msb lsb data byte 0 op-code byte figure 6. 2-byte spi write example csn so si sck spi mode 0 msb lsb 0 12 3 4 5 67 high z 0 12 3 4 5 670 12 3 4 5 67 msb lsb msb lsb data byte 1 data byte 0 op-code byte note: spi instruction op-codes not shown in table 2 are reserved and must not be used. further, these op-codes will not provide meaningful data in response to a read instruction. two instruction bytes cannot be chained; csn must be negated after each instruction, and then reasserted for the following read or write instruction. holt integrated circuits 5 hi-8435 figure 7. 4-byte spi read example csn so si sck spi mode 0 msb lsb 0 12 3 4 5 67 high z 0 12 3 4 5 670 12 3 4 5 67 msb lsb msb lsb data byte 3 data byte 2 op-code byte 0 12 3 4 5 670 12 3 4 5 67 msb lsb msb lsb data byte 1 data byte 0
register descriptions holt integrated circuits 6 hi-8435 table 3. 7-2 - 1 srst 0 test bit name r/w default description r/w 0 not used. r/w 0 software reset - setting this bit to 1 holds all other registers and the test bit to their reset values. srst bit must be written back to 0 to release this reset . r/w 0 setting this bit to 1 puts the hi-8435 in the self test mode. input to sensors are internally set according to the value of the test mode data register 76543210 msb lsb srst test control register : ctrl read: spi op-code 0x82 write: spi op-code 0x02 reset value 00 [opcode, db0] x xxxxx table 4. 7-4 - r/w 0 3-0 bank3-0 bit name r/w default description not used. r/w 0 program sensor type for sense inputs. bank 0 programs inputs sense<7:0> bank 1 programs inputs sense<15:8> bank 2 programs inputs sense<23:16> bank 3 programs inputs sense<31:24> setting a bit to 0 programs the 8 inputs in the bank to be gnd/open sensors. setting a bit to 1 programs the 8 inputs in the bank to be supply/open sensors. table 5. 76543210 msb lsb bank1 bank0 program sense banks register: psen<3:0> read: spi op-code 0x84 write: spi op-code 0x04 reset value 00 [opcode, db0] bank2 bank3 xxxx data byte 0 data byte 0 odd1 = 1 odd inputs are set high odd0 = 1 odd inputs are set low all1 = 1 all inputs are set high all0 = 1 all inputs are set low bit name r/w default description 7-4 - r/w 0 not used. 3-0 tmdata3-0 r/w 0 these 4 bits program the internal inputs to the sense comparators when in the test mode. note: only one mode can be selected. if more than one bit is high the inputs will all be set low. 76543210 msb all1 all0 test mode data register : tmdata read: spi op-code 0x9e write: spi op-code 0x1e reset value 00 [opcode, db0] odd0 odd1 x x x data byte 0 x
hi-8435 holt integrated circuits 7 register descriptions (cont.) table 6. bit name r/w default description data word 1 7-6 - r/w 0 not used. 5-0 gohys5-0 r/w 0 gnd/open hysteresis. for all inputs programmed to be gnd/open sensors the hysteresis is set by these 6 bits. hysteresis = 1v x gohys value. data word 0 7-6 - r/w 0 not used. 5- 0 gocval5-0 r/w 0 gnd/open threshold center value. for all inputs programmed to be gnd/open sensors the center threshold is set by these 6 bits. center threshold = 0.5v x gocval value. vthi = threshold center valu e + ? hysteresis, max limit = 22v, min limit = 3v vtlo = threshold center valu e - ? hysteresis, max limit = 21v, min limit = 2v example: gnd/open sensors with vthi = 10.5v and vtlo = 4.5v: a) program gohys hysteresis = vthi - vtlo = 10.5v - 4.5v = 6v = 0x06 b) program gocval center value = (vthi + vtlo)/2 = (10.5v + 4.5v)/2 = 7.5v since the dac gain = 0.5v/1code, converting the center value voltage to code, the formula reduces to: center value (in code value) = vthi + vtlo = 15 codes = 0x0f c) write 0x3a 0x06 0x0f to spi 0x3a writes to the gnd/open threshold and hysteresis register. 0x06 is 6 decimal = 6v hysteresis. 0x0f is 15 decimal x 0.5v = 7.5v center threshold. vthi = 7.5v + 3v = 10.5v vtlo = 7.5v - 3v = 4.5v note: the maximum value for vthi = 22v and the minimum value for vtlo = 2v. also vthi - vtlo >= 1v. 76543210 msb lsb gohys1 gohys0 gnd/open threshold center value and hysteresis register: gocenhys read: spi op-code 0xba write: spi op-code 0x3a reset value 00 [opcode, db1 , db0] gohys2 gohys3 gohys4 76543210 msb lsb gocv al1 gocval0 gocv al2 gocv al3 gocv al4 data byte 1 data byte 0 x x x x gocv al5 gohys5
hi-8435 holt integrated circuits 8 register descriptions (cont.) table 7. data word 1 bit name r/w default description 7-6 - r/w 0 not used. 5-0 sohys5-0 r/w 0 supply/open hysteresis. for all inputs programmed to be supply/open sensors the hysteresis is set by these 6 bits. hysteresis = 1v x sohys value. data word 0 7-6 - r/w 0 not used. 5- 0 socval5-0 r/w 0 supply/open threshold center value. for all inputs programmed to be supply/open sensors the center threshold is set by these 6 bits. center threshold = 0.5v x socval. vthi = threshold center valu e + ? hysteresis, max limit = 22v, min limit = 3v vtlo = threshold center valu e - ? hysteresis, max limit = 21v, min limit = 2v example: supply/open sensor with vthi = 12v and vtlo = 6v: a) program sohys hysteresis = vthi - vtlo = 12v - 6v = 6v = 0x06 b) program socval center value = (vthi + vtlo)/2 = (12v + 6v)/2 = 9v since the dac gain = 0.5v/1code, converting the center value voltage to code, the formula reduces to: center value (in code value) = vthi + vtlo = 18 codes = 0x12 c) write 0x3c 0x06 0x12 to spi 0xbc writes to the supply/open threshold and hysteresis registers. 0x06 is 6 decimal = 6v hysteresis. 0x12 is 18 decimal x 0.5v = 9v center threshold. vthi = 9v + 3v = 12v vtlo=9v-3v = 6v note: the maximum value for vthi = 22v and the minimum value for vtlo = 2v. also vthi - vtlo >= 1v. 76543210 msb lsb sohys1 sohys0 supply/open threshold center value and hysteresis register: socenhys read: spi op-code 0xbc write: spi op-code 0x3c reset value 00 [opcode, db1, db0] sohys2 sohys3 sohys4 76543210 msb lsb socv al1 socval0 socv al2 socv al3 socv al4 data byte 1 data byte 0 x x x x socv al5 sohys5
hi-8435 holt integrated circuits 9 register descriptions (cont.) table 10. 7-0 so<23:16> r 0 sensor output status, so<23:16> reports the state of sense<23:16>. bit name r/w default description 76543210 msb lsb so<17> so<16> read: spi op-code 0x94 write: na, read only reset value 00 [opcode, db0] sensor status bank 2 register: so<23:16> so<18> so<19> so<20> so<21> so<22> so<23> sensor output status register: so<31:0> this 32 bit register is accessed by the following 5 spi commands for gnd/open inputs, so = 0 if the sense pin is open or > vthi so = 1 if the sense pin is <= vtlo for supply/open inputs, so = 1 if the sense pin is open or < vtlo so = 0 if the sense pin is >= vthi table 11. 7-0 so<31:24> r 0 sensor output status, so<31:24> reports the state of sense<31:24>. bit name r/w default description 76543210 msb lsb so<25> so<24> read: spi op-code 0x96 write: na, read only reset value 00 [opcode, db0] sensor status bank 3 register: so<31:24> so<26> so<27> so<28> so<29> so<30> so<31> data byte 0 data byte 0 7-0 so<15:8> r 0 sensor output status, so<15:8> reports the state of sense<15:8>. bit name r/w default description table 9. 76543210 msb lsb so<9> so<8> read: spi op-code 0x92 write: na, read only reset value 00 [opcode, db0] sensor status bank 1 register: so<15:8> so<10> so<11> so<12> so<13> so<14> so<15> data byte 0 read: spi op-code 0x90 write: na, read only reset value 00 [opcode, db0] sensor status bank 0 register: so<7:0> 7-0 so<7:0> r 0 sensor output status, so<7:0> reports the state of sense<7:0>. bit name r/w default description 76543210 msb lsb so<1> so<0> so<2> so<3> so<4> so<5> so<6> so<7> table 8. data byte 0
hi-8435 holt integrated circuits 10 register descriptions (cont.) table 12. 31-0 so<31:0> r 0 sensor output status, so<31:0> reports the state of sense<31:0>. bit name r/w default description read: spi op-code 0xf8 write: na, read only reset value 00 [opcode, db3, db2, db1, db0] sensor status all banks register: so<31:0> 76543210 msb lsb so<25> so<24> so<26> so<27> so<28> so<29> so<30> so<31> 76543210 msb lsb so<17> so<16> so<18> so<19> so<20> so<21> so<22> so<23> 76543210 msb lsb so<9> so<8> so<10> so<1 1> so<12> so<13> so<14> so<15> 76543210 msb lsb so<1> so<0> so<2> so<3> so<4> so<5> so<6> so<7> data byte 3 data byte 2 data byte 1 data byte 0 spi format examples msb lsb 0 0 1 0 0 0 0 1 1 0 1 1 1 data word bits spi op-code example 1. single data byte, read sense data in sense bank 0 . (op-code 0x90) 1 1 so<1> so<0> so<2> so<3> so<4> so<5> so<6> so<7> lsb msb data byte 0 example 2. double data byte, write gnd/open threshold center value and hysteresis . (op-code 0x3a) msb lsb 0 0 0 1 1 1 1 0 0 0 1 1 0 0 0 0 hysteresis value 0 spi op-code msb lsb 011 10 10 threshold center value gohys1 gohys0 gohys2 gohys3 gohys4 lsb data byte 1 lsb msb data byte 0 gocv al1 gocval0 gocv al2 gocv al3 gocv al4 gocv al5 example 3. 4 data byte, read all sense values, sense all banks . (op-code 0xf8) msb lsb 1 1 0 1 0 0 0 0 1 1 1 1 spi op-code msb lsb 111 10 00 msb lsb 0 0 1 1 1 0 0 1 1 0 0 0 1 1 0 0 0 0 0 so<1> so<0> so<2> so<3> so<4> so<5> so<6> so<7> so<9> so<8> so<10> so<11> so<12> so<13> so<14> so<15> so<17> so<16> so<18> so19> so<20> so<21> so<22> so<23> so<25> so<24> so<26> so<27> so<28> so<29> so<30> so<31> 1 0 data byte 3 data byte 2 data byte 1 data byte 0 lsb msb msb lsb table 13. gohys5 0
functional description hi-8435 holt integrated circuits 11 overview the hi-8435 is comprised of 32 sensors arranged in 4 banks of 8 inputs, easily accessible via a four wire spi communication bus. each bank of sensors can be programmed as either gnd/open or supply/open. the state of each sensor can be read out through the spi. the gnd/open high/low thresholds can be programmed independently of the supply/open high/low thresholds. an internal test mode is available which sets the input to each sensor comparator to the test value as programmed by the test mode data register. table 14 summarizes basic function selection and table 16 gives more details on possible threshold values. the hi-8435 generates a full reset upon application of power. this power-on-reset (por) sets all registers to their default values. the part can also be initialized to the full reset state by applying a 100ns active low pulse to the external mrb pin. a software reset is also possible via the spi by writing a 1 to cntrl<1>. this reset is the same as the full reset except the part is held in the reset mode until the cntrl<1> bit is written back to a 0. the user configures the hi-8435 for specific applications by: 1) programming the sensor type for each of the 4 banks. 2) convert the required vthi and vtlo into center and hysteresis values as shown in example below. 3) for gnd/open sensors, vwetn must be set greater than vthi/0.9 + 2.25v. the hi-8435s on-chip dac takes the 6-bit programmed center and hysteresis values from the threshold center value and hysteresis registers (gocenhys and socenhys) and converts them to vthi and vtlo values. maximum and minimum values may be found in table 16. the gain of the dac is 0.5v per bit. vthi = center value + ? hysteresis vtlo = center value - ? hysteresis initialization and reset configuration programming thresholds to program the thresholds: a) select vthi and vtlo. b) hysteresis = vthi - vtlo. c) center value = (vthi - vtlo)/2 x 2codes/v = vthi + vtlo codes d) program the register. example: a) gnd/open, for vthi = 10.5v and vtlo = 4.5v b) hysteresis = vthi - vtlo = 10.5 - 4.5 = 6v = 0x06 c) center value = vthi + vtlo = 15 codes = 0x0f d) program gocenhys register: 0x3a 0x06 0x0f for gnd/open sensing, the psenn bit is set to 0. referring to the block diagram, figure 2, this selection will connect a 3.3k pull-up resistor through a diode to vlogic. this resistor gives extra noise immunity for detecting the open state while providing relay wetting current. the user programs the desired threshold/hysteresis levels and then determines the open input voltage to set vwetn. for correct operation, the v when open, must be higher than so so_n will be low. this condition requires vwet to be set greater than (vthi/0.9 + 2.25v) he standard open signal as characterized by a resistance of 100k or more with respect to signal common. the user should consider this 100k to ground case when setting the thresholds. gnd/open sensing open input voltage sense_n thi v . various arinc standards such as arinc 763 define t sense_n psen_n so_n vwet_n open or > vthi l (gnd/open) l ** < vtlo l (gnd/open) h ** open or < vtlo h (v+/open) h open > vthi h (v+/open) l open h = vlogic, l = gnd vthi = threshold center valu e + ? hsyteresis vtlo = threshold center valu e - ? hysteresis **for gnd/open applications vwetn must be set greater than vthi/0.9 + 2.25v function table table 14. function table
functional description (cont.) hi-8435 holt integrated circuits 12 wetting current threshold select when applying a higher voltage at vwet,_n the wetting cur- rent is (vlogic - 0.75)/3.3k + (vwet - 4.2)/127k. additional wetting current can be achieved by placing an ex- ternal resistor and a diode between vwet_n and the indi- vidual sense inputs. when programmed as supply/open sensors, psen_n is set to a logic 1. referring to figure 2, a 32k resistor in series with a diode is switched to provide a pull down in addition to the 400k of the comparator input divider to gnd. the user programs the desired threshold and hysteresis levels. vwet_n must be left open for any bank that is programmed as supply/open sensors. the threshold selections are handled the same was as stated above for the gnd/open case. see table 16 for maxi- mum and minimum values. example: a) supply/open, for vthi = 12v and vtlo = 6v b) hysteresis = vthi - vtlo = 12 - 6 = 6v = 0x06 c) center value = vthi + vtlo = 18 codes = 0x12 d) program socenhys register: 0x3c 0x06 0x12 supply/open sensing wetting current for the v+/open case the wetting current into the sense input is simply the current sunk by the effective 30k to gnd. for v = 28v, i is 1ma. see figure 8. writing a high in ctrl<0> puts the hi-8435 into the test mode. referring to figure 2, when in the test mode each of the internal inputs to the sense comparators are set to either a high or low. since the input sense pin is isolated by a 360k resistor, this test mode will not disturb the actual status of the input pin. by programming the test mode data register, one of four input data patterns can be selected. see table 5 on page 6 for options. the comparator results are read through the spi just as in normal operation. before entering test mode the sensors must be programmed with valid threshold values. sense_n wet test mode figure 8. input current vs. input voltage
functional description (cont.) hi-8435 holt integrated circuits 13 figure 9. multiple chip connection 96 channel sensor application using hi-8435 host controller so si sck gp1 gp2 gp3 sck csn si so hi - 8435 device 1 sense<31-0> sck csn si so hi - 8435 device 2 sense<31-0> sck csn si so hi - 8435 device 3 sense<31-0> 32 32 32 csn_1 csn_2 csn_3 so si sck from sense inputs 31-0 from sense inputs 63-32 from sense inputs 95-64
functional description (cont.) hi-8435 holt integrated circuits 14 lightning protection all sense_n inputs are protected to rtca/do-160g, section 22, categories az and bz, waveforms 3, 4, 5a, with no external components. in addition, all inputs are also protected to zz, waveforms 3 and 5b, to provide more robustness in composite airframe applications. table 15 and figure 10 give values and waveforms. figure 10. lightning waveforms table 15. waveform peak amplitudes level waveforms 3/3 4/1 5a/5a voc (v) / isc (a) voc (v) / isc (a) voc (v) / isc (a) 2 250/10 125/25 125/125 z 500/20 300/60 300/300 3 600/24 300/60 300/300 5b/5b voc (v) / isc (a) 125/125 300/300 300/300 0.0 0.3 0.5 0.8 1.0 voltage waveform 4 t2 t1 v(%) t1 = 6.4s +/-20% t2 = 69s +/-20% t 50% peak 0.0 0.3 0.5 0.8 1.0 current/voltage waveform 5a t2 t1 i/v (%) t1 = 40s +/-20% t2 = 120s +/-20% t 50% peak -1.0 -0.5 0.0 0.5 1.0 t voltage/current waveform 3 peak 50% v/i (%) 1us/div. 0.0 0.3 0.5 0.8 1.0 current/voltage waveform 5b t2 t1 i/v (%) t1 = 50s +/-20% t2 = 500s +/-20% t 50% peak
functional description (cont.) hi-8435 holt integrated circuits 15 figure 11: threshold tolerance over programmed value vlogic psenn operation vwet pin programmed vthi programmed vtlo guaranteed high threshold* guaranteed low threshold* 3.0v to 3.6v 7v gnd/open l 4.0v 2.0v vthi + 0.5v vtlo - 0.5v 3.0v to 3.6v 28v gnd/open l 22v 2.0v vthi + 1.25v vtlo - 0.5v 3.0v to 3.6v open v+/open h 22v 2.0v vthi + 1.25v vtlo - 0.5v note: vthi = center value + 0.5 x hysteresis, vtlo = center value - 0.5 x hysteresis *: see figure 11 for guaranteed tolerance for programmed vthi and vtlo table 16. configuration examples and allowed threshold values -55c to 125c. 0 5 10 15 20 25 0 5 10 15 20 25 vthi or vtlo (v) threshold tolerance min limit max limit programmed voltage (v)
note: stresses above absolute maximum ratings or outside recommended operating conditions may cause permanent damage to the device. these are stress ratings only. operation at the limits is not recommended. absolute maximum ratings recommended operating conditions d.c. electrical characteristics vdd = 3.3v, gnd = 0v, t = operating temperature range (unless otherwise specified). a hi-8435 holt integrated circuits 16 supply voltage vlogic ................................. 3.0v to 3.6v vwet_n ................................. 7.0v to 36v digital inputs .......................... 0 to vlogic sense_n ............................... -4.0v to 36v operating temperature range industrial screening ............. -40c to +85c hi-temp screening ............. -55c to +125c parameter sym condition min typ max units discrete inputs sense v+/open resistance to ground r in 30 k threshold dac gain v thac 1 dac bit = 0.5v. guaranteed monotonic 0.5 v/bit max threshold high (v+ state input voltage) v thimax vthi = center valu e + ? hysteresis input voltage to give low output vthi - vtlo 1v refer to figure 11 v min threshold low (open state input voltage) v tlomin vtlo = center valu e - ? hysteresis input voltage to give high output vthi - vtlo 1v refer to figure 11 v input current at 28v i in28 v = 28v in 0.95 ma voltages referenced to ground supply voltage (vlogic) ......................... -0.3v to +7v vwetn .......................... -0.3v to +80v discrete input voltage range (dc) ................... -80v to +80v (ac, 60 - 400hz) ................... 115vrms continuous power dissipation (ta=+70c) qfn (derate 21.3mw/c above +70c) ........ 1.7w qfp (derate 10.0mw/c above +70c) ........ 1.5w solder temperature (reflow) ............................. 260c junction temperature ............................. 175c storage temperature ............................ -65c to -150c logic input voltage range ................ -0.3v to vlogic+0.3v
hi-8435 holt integrated circuits 17 d.c. electrical characteristics (cont) vdd = 3.3v, gnd = 0v, t = operating temperature range (unless otherwise specified). a logic inputs input voltage v ih input voltage hi 70% vlogic v il input votage lo 30% vlogic input current, si i sink v = vlogic, 30k pull down in 125 a i source v = gnd in 0.1 a input current, mrb, csn i sink v = vlogic in 0.1 a i source v = gnd , 30k pull up in 125 a logic outputs output voltage v oh i = -100 a oh 90% vlogic v ol i = 100 a ol 10% vlogic output current i ol v = 0.4v out 1.6 ma i oh v = vlogic - 0.4v out -1.0 ma output capacitance c o 15 pf parameter sym condition min typ max unit discrete inputs sense gnd/open resistance in series with diode to vlogic r in 3.3 k resistance in series with diode to vwet r w 28 k threshold dac gain v tdg 1 dac bit = 0.5v. guaranteed monotonic 0.5 v/bit max threshold high (open state input voltage) v thimax vthi = center valu e + ? hysteresis input voltage to give low output vthi - vtlo 1v refer to figure 11 v min threshold low (ground state input voltage ) v tlomin vtlo = center valu e - ? hysteresis input voltage to give high output vthi - vtlo 1v refer to figure 11 v input current at 0v i in0 v = 0v, vwet = open in -0.65 ma supply operating vlogic range vlogic 3.0 3.6 v operation vwet range vwet 728v vlogic current i dd1 all sense pins open 15 ma vwetn current i vwetn all inputs for bank = 0v, vwetn = 28v 35 ma
ac electrical characteristics vdd = 3.3v, ta = operating temperature range hi-8435 parameter symbol limits units min typ max spi interface timings sck clock period t cyc 50 ns cs active after last sck rising edge t chh 5ns cs setup time to first sck rising edge t ces 5ns cs hold time after last sck falling edge t ceh 5ns cs inactive between spi instructions t cph 55 ns spi si data set-up time to sck rising edge t ds 10 ns spi si data hold time after sck rising edge t dh 10 ns sck rise time t sckr 10 ns sck fall time t sckf 10 ns sck pulse width high t sckh 20 ns sck pulse width low t sckl 20 ns so valid after sck falling edge t dv 20 ns so high-impedance after sck falling edge t chz 20 mr pulse width t mr 100 ns sensor timings delay, change at sense input to valid status in so_n 1s delay, change of threshold to valid status in so_n 1s holt integrated circuits 18 figure 13. spi serial output timing cs sck so chz t hi impedance sckh t t dv lsb cph t t sckl msb hi impedance cyc t cs sck si chh t ceh t msb ces t ds tt dh lsb cph t sckr t sckf t cyc t figure 12. spi serial input timing
hi-8435 hi - 8435xx x x ordering information holt integrated circuits 19 part number package description 8435pq 44 pin plastic quad flat pack, pqfp (44pmqs) 8435pc 44 pin plastic chip-scale, qfn (44pcs) part number temperature range flow burn in i -40c to +85c i no t -55c to +125c t no part number lead finish blank tin / lead (sn /pb) solder f 100% matte tin (pb-free, rohs compliant)
p/n rev date description of change ds8435 new 02/05/13 initial release. a 06/14/13 added threshold tolerance curve (figure 11) to clarify guaranteed threshold limits. updated text references to limits accordingly. b 06/20/13 corrected typo for vwet min. in dc electrical characteristics. clarified hysteresis value (vthi - vtlo) dc electrical characteristics. c 07/03/13 updated absolute maximum ratings table for vwetn and discrete input voltage range parameters. clarified value of vwetn for gnd/open applications in table 14. added mil-std-704 compliance to features. 1vin revision history holt integrated circuits 20 hi-8435
package dimensions holt integrated circuits 21 44-pin plastic chip-scale package (qfn) inches (millimeters) package type: 44pcs bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95) .216 .002 (5.5 .05) .016 .002 (0.40 .05) .010 (0.25) .020 (0.50) .008 (0.2) .039 (1.00) .276 (7.00) bsc .216 .002 (5.5 .05) typ typ bottom view top view bsc .276 (7.00) bsc max electrically isolated pad on bottom of package. connect to any ground or power plane for optimum thermal dissipation. package type: 0 7 detail a see detail a sq. 44pmqs 44-pin plastic quad flat pack (pqfp) .009 (.23) .520 .010 (13.20 .25) .394 .004 (10.0 .10) sq. max. .014 .003 (.37 .08) .035 .006 (.88 .15) .005 (.13) r min. .012 (.30) r max. .079 .008 (2.0 .20) .096 (2.45) max. .0315 (.80) inches (millimeters) bsc bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95)

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